1. Field of the Invention
The present invention presents a method of dynamically storing a flash translation layer of a solid state module, more particularly, a method of dynamically storing a flash translation layer of a solid state module according to an efficiency of the flash translation layer of each of the solid state disks of the solid state module.
2. Description of the Prior Art
A solid state disk (SSD) is a memory formed using a NAND flash memory array. The NAND flash memory array has a finite number of erase cycles. Because of the finite number of erase cycles, the information is stored separately and flash translation layers (FTL) are used to establish a mapping table for the logical address and the physical address of the information. The mapping table is used to manage the relationship between the logical address and the physical address of the information when the information is being accessed. A plurality of solid state disks are then used to form a solid state module for increasing memory capacity.
FIG. 1 illustrates a storage system 1 of an electronic device according to prior art. The electronic device may be a computer, a cellphone, etc. The host 2 of the storage system 1 has a central processing unit 3 fitted with a dynamic random access memory (DRAM) 4 used to transmit the logical address of the accessed information to a transfer interface 5 for outputting. A solid state module 6 uses a host bus adaptor (HBA) 7 to the transfer interface 5 to process the logical address of the accessed information received from the host 2. After the host bus adaptor 7 has processed the logical address, the host bus adaptor 7 transmits the logical address to a port multiplier 8. The port multiplier 8 is configured to distribute the logical address to the plurality of solid state disks 9, 10, and 11. The controllers 12, 13, and 14, each coupled to a corresponding solid state disk 9, 10, and 11, coordinate with a buffer memory 15 and 16 during processing. The information is accessed from the physical address of the NAND flash memories 17, 18, and 19 in each of the solid state disks 9, 10, and 11 corresponding to the logical address. The information is then stored in the dynamic random access memory 4 of the host 2 for future use.
For each of the solid state disks 9, 10, and 11 to be able to manage the relation between the logical address of the information and the physical address of the NAND flash memories 17, 18, and 19 where the information is stored, during the operation of each of the solid state disks 9, 10, and 11, the management data of each information block in the NAND flash memories 17, 18, and 19 is read separately. The mapping table of the logical address and the physical address of the information is formed by establishing flash translation layer to store and manage the mapping table. To establish the position of the flash translation layer, during the initialization of the solid state disks, the firmware stored in each of the NAND flash memories may be preset in the buffer memories or the NAND flash memories and may not be changed.
The size of the conventional solid state disk is dependent on the buffer memory. The following are modes of establishing position of the flash translation layer: The first mode is illustrated the solid state disk 9 shown in FIG. 1. For establishing the flash translation layer, when the size of the buffer memory 15 is not less than the estimated size of the mapping table, the establishing position 20 of the flash translation layer may be entirely set in the buffer memory 15. The full logical-to-physical (L2P) table mapping method is selectively used. The second mode is illustrated the solid state disk 10 shown in FIG. 1. When the size of the buffer memory 16 is less than the estimated size of the mapping table, the establishing position 21 of the flash translation layer may be partially set in the buffer memory 16 and the remaining part is established in the NAND flash memory 18. The partial L2P table mapping method is selectively used. The third mode is the solid state disk 11 shown in FIG. 1. When there is no buffer memory 16 set, the establishing position 22 of the flash translation layer may be entirely set in the NAND flash memory 19. The full array L2P table mapping method is selectively used.
Because the accessing speed of the dynamic random access memory is 10 times faster than NAND flash memory and the buffer memories 15 and 16 are dynamic random access memories, the accessing speed of the buffer memories 15 and 16 are faster than the NAND flash memories 17, 18, and 19. In consideration of the lifespan of the NAND flash memory, the information is scattered during storage. When each of the solid state disks of the solid state module 6 is in full storage mode, the flash translation layer is set in the buffer memory for the transmission speed of the flash translation layer to be fast, the accessing speed of each of the solid state disks to be equal to each other, the information to be gathered without waiting too long, and for the efficiency of accessing information to be at optimal.
However, each of the solid state disks of the conventional solid state module 6 has a flash translation layer that is set to different storage mode. More particularly, the consistency of the storage mode of the expandable solid state module 6 before and after the addition of the solid state disk is hard to maintain. When information of a file is scattered in solid state disks 9, 10, 11 having different storage modes, the solid state disk 9 using the full L2P table mapping method completes the accessing of information the fastest, the solid state disk 10 using the partial L2P table mapping method completes the accessing of information in 5 times the time needed by the solid state disk 9, and the solid state disk 11 using the full array L2P table mapping method completes the accessing of information in 10 times the time needed by the solid state disk 9. The host needs to wait for the solid state disk 11 to complete accessing before the information is completely accessible. Thus, decreasing the efficiency of the accessing the solid state module 6. Therefore, there is a need to improve the method of storing the flash translation layer of the solid state module.